IMAGE: Bryan Christie Design

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Having built well-functioning transistors using old technology, in the second half of 2003 it was time to move from research to development of high-k dielectric plus metal gate transistors, as we called them. Engineers began working to determine whether these early transistors could be scaled to the ­upcoming 45-nm dimensions and still meet the rigorous performance, reliability, and manufacturability requirements of an advanced microprocessor technology.

It was no cakewalk. The research group engineers had provided a critical lead in identifying promising high-k and metal gate materials, but the NMOS and PMOS transistors had not yet been combined on one wafer as they would be in a microprocessor, using a manufacturing process that could make both. What's more, there were hard questions still to be answered about how many good chips we could expect for every bad one (yield) and how reliable those chips would be.

During the months that followed, the team cracked one problem after another—making changes to materials, chemical recipes, and manufacturing processes. It wasn't until late 2004 that the team felt it had enough convincing data that the new transistors could be made to work on our 45-nm technology. At that point, there was no turning back. Intel was now committed to making a high-k dielectric plus metal gate transistor structure using the gate-last process flow. It was a gutsy call. Our team knew it was committing all of Intel's next generation of microprocessors to the biggest change in transistor technology in 40 years.

The next key milestone was to demonstrate working test chips using the final scaled dimensions combined with the new transistor features. The traditional chip to test a new technology on is static random access memory, or SRAM, which is the type of memory collocated on the same chip with the micro­processor. Typically, microprocessor makers have designs for SRAM that are a year or more ahead of their processor designs. SRAM is a very regular array of memory cells, each of which consists of six densely packed and interconnected transistors. Because of their density and regularity, SRAM chips provide good data on how many defects a manufacturing process produces.

Our first fully functional test SRAM chips with the new transistors came off the line in January 2006. They were of a 153-­megabit design consisting of more than 1 ­billion transistors. Each six-­transistor memory cell in the chip occupied little more than one-third of a square micrometer. This test chip had all the features needed to build a 45-nm micro­processor, including the high-k plus metal gate transistors and nine layers of copper interconnects. Considering how new and radically different the transistor and manufacturing process were, it was a surprise even to some of the engineers in the development group that it all worked together so well. Even so, the development team still had a lot ahead of it to bring the performance, reliability, and yield of the process up to the level needed for manufacturing microprocessors.

The new gate stack worked wonders in battling leakage through the gate, reducing it by more than a factor of 10. But the gate oxide is not the only source of transistor leakage chip makers have to worry about. The other significant leak is called source-to-drain or subthreshold leakage. It's a trickle of current seen even when the transistor is intended to be in the “off” state. Making transistors smaller has also meant steadily lowering the amount of voltage needed to turn them on, the threshold voltage. Unfortunately, steadily lowering the threshold voltage lets more current slip through. For many years, each new generation of transistor would increase drive current (and improve performance) by about 30 percent but would pay the price of about a threefold increase in subthreshold leakage. Leakage currents have reached levels high enough to be a noticeable portion of total microprocessor power consumption.

The industry is now in an era where power efficiency and low leakage are more important than raw speed increases. But a transistor can be designed to operate to favor either priority by adjusting the channel length or adjusting the threshold voltage. A shorter channel leaks more but allows for a higher drive current. A higher threshold voltage pinches off the leak but also throttles the drive current. Adjusting the threshold voltage is where the high-k dielectric comes into play. A thicker dielectric reduces the gate's ability to open a conductive channel between the source and the drain, increasing the ­threshold voltage. A thinner dielectric layer has the opposite effect. Compared with the previous 65-nm transistors, 45-nm high-k plus metal gate transistors provide either a 25 percent increase in drive current at the same subthreshold leakage or more than a fivefold reduction in leakage at the same drive current, or anywhere between those values. We can make the choice on a product-by-product basis, or different circuits on the same microprocessor chip can use different transistors to optimize for performance or power.

In January 2007, Intel made the first working 45-nm micro­processors using these revolutionary high-k plus metal gate transistors. One was the Penryn dual-core microprocessor, which has 410 million transistors. Different versions of Penryn will be optimized for mobile, desktop, workstation, and server applications. The quad-core version of this product will have 820 million transistors. Penryn was followed a few months later by Silverthorne, a single-core microprocessor with 47 million transistors that is designed for low-power applications, including mobile Internet devices and ultramobile PCs. There are more than 15 new chips under development at Intel using our new technology. Production of Penryn and Silverthorne will start later this year at Intel plants in Oregon and Arizona. Next year, we'll start up the process at two other high-volume manufacturing fabs, in New Mexico and Israel.

The invention of high-k plus metal gate transistors was an important breakthrough. Although we could have continued to shrink transistors to fit the dimensions needed for the 45-nm generation without this breakthrough, those transistors would not have worked much better than their predecessors, and they certainly would have expended more watts. We're confident this new transistor can be scaled further, and development is already well under way on our next-generation 32-nm transistors using an improved version of high-k plus metal gate technology. Whether this type of transistor structure will continue to scale to the next two generations—22 nm and 16 nm—is a question for the future. Will we need new materials and new structures again?

Nobody knows for sure. But that is what makes integrated circuit research and development so exciting.