IMAGE: Intel

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We set about studying a veritable alphabet soup of high-k dielectric candidates, including aluminum oxide (Al₂O₃), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), hafnium dioxide (HfO₂), hafnium silicate (HfSiO₄), zirconium oxide (ZrO₂), zirconium silicate (ZrSiO₄), and lanthanum oxide (La₂O₃). We were trying to identify such things as the material's dielectric constant, how electrically stable it was, and its compatibility with silicon. For quick turnaround, we experimented with simple capacitor structures, building a sandwich consisting of titanium nitride electrodes, the high-k dielectric, and a silicon gate electrode. We then charged them up and discharged them again and again, watching to see how much the relationship between capacitance and voltage changed with each cycle.

But for the first two years, all the dielectrics we tried worked poorly. We found that charges got trapped at the interface between the gate electrode and the dielectric. This accumulated charge within the capacitor altered the voltage level needed to store the same amount of energy in the capacitor from one charge-discharge cycle to the next. You want a transistor to operate exactly the same way every time it switches, but these gate-stack structures behaved differently each time they were charged up. The results were very discouraging, but eventually our team got an important break.

It turned out that the problem lay in how we constructed the test capacitor. To make the dielectric layer, we were using one of two different semiconductor-manufacturing techniques: reactive sputtering and metal organic chemical vapor deposition. Unfortunately, both processes produce surfaces that, though remarkably smooth by most standards, were nevertheless uneven enough to leave some gaps and pockets in which charges could get stuck.

We needed something even smoother—as smooth as a single layer of atoms, actually. So we turned to a technology called atomic layer deposition, so new that its debut in CMOS chip production comes only this year with our new high-k chips. Atomic layer deposition lets you build up a material one layer of atoms at a time. In this process, you introduce a gas that reacts with the surface of the silicon wafer, leaving the whole substrate coated in a single layer of atoms. Then, because there is no more surface to react with, the deposition stops. The gas is evacuated from the chamber and replaced with a second gas, one that chemically reacts with the layer of atoms just deposited. It too lays down one layer of atoms and then stops. You can repeat the process as many times as you want, to produce layered materials whose total thickness is controllable down to the width of a single atom.

Deposited in this manner, both the hafnium- and ­zirconium-based high-k dielectrics we studied showed much more stable electrical characteristics in comparison with the ones formed by ­sputtering or chemical vapors. The trapped-charge problem seemed to have been smoothed out.

With two candidate materials identified, we started making NMOS and PMOS transistors out of them. Then came the next snag. These transistors, pretty much identical to our existing transistors except for the different dielectric, had a few problems. For one thing, it took more voltage to turn them on than it should have—what's called Fermi-level pinning. For another, once the transistors were on, the charges moved sluggishly through them—slowing the device's switching speed. This problem is known as low charge-carrier mobility.

We weren't the only ones encountering these problems; just about everybody else was struggling with them, too. With the countdown in progress for the next generation predicted by Moore's Law, understanding why the high-k dielectric transistors performed so poorly and finding a solution became an urgent task. Using a combination of experimental work and physics-based models, we began to figure out what had gone wrong. The source of the trouble, ultimately, came down to the interaction between the polysilicon gate electrode and the new high-k dielectrics.

Why this is so has a complicated explanation. The dielectric layer is made up of dipoles—objects with a positive pole and a negative one. This is the very aspect that gives the high-k dielectric such a high dielectric constant. These dipoles vibrate like a taut rubber band and lead to strong vibrations in a semiconductor's crystal lattice, called phonons [see illustration, “Bumpy Ride”]. These phonons knock around passing electrons, slowing them down and reducing the speed at which the transistor can switch. But theoretical studies and computer simulations performed by us and others showed a way out. The simulations indicated that the influence of dipole vibrations on the channel electrons can be screened out by significantly increasing the density of electrons in the gate electrode. One way to do that would be to switch from a polysilicon gate to a metal one. As a conductor, metal can pack in hundreds of times more electrons than silicon. Experiments and further computer simulations confirmed that metal gates would do the trick, screening out the phonons and letting current flow smoothly through the transistor channel.

What's more, the bond between the high-k dielectric and the metal gate would be so much better than that between the dielectric and the silicon gate that our other problem, Fermi-level pinning, would be solved by a metal gate as well.