Photo: Chris Mueller

Chip Guru: Dan Edelstein is leading the second revolution in chip interconnects.

The industry has been insulating microchip conductors with silicon dioxide (glass, basically) since the first commercial integrated circuits were introduced in 1961. For years, the wires that carry the electrical current on a chip were barely an afterthought. “The transistor was everything,” says Edelstein.

But by 2000, joining the millions of transistors into a functioning integrated circuit necessitated nearly 2 km of wire. Nobody wants wider chips (space on a circuit board is always tight), so the only way to pack in all that wiring is to make them taller. To do that, individual wiring levels—each consisting of the glasslike insulating material inlaid with a network of the copper wiring—are stacked on top of each other by a process called dual ­damascene, named for the ancient Middle Eastern method of inlaying gold or silver into a sword.

To build the stack, the base level—the dinner-plate-size wafer containing the transistors—is first covered with a layer of insulation made of an impure glass variant. A pattern is transferred onto it by photolithography, which is similar to photography: the insulation is covered with a light-­sensitive material called a photoresist, onto which a pattern is projected, using ultraviolet light streaming through a mask. When the light hits the exposed areas of the photo­resist, it changes the material’s chemical properties: the area in the mask’s shadow remains strong and corrosion resistant, but the area exposed to light has become vulnerable. A corrosive plasma eats away the vulnerable areas and the insulation beneath, creating a network of trenches.

Now this level is ready for its wiring. First, the glass is lined with a thin, corrosion-resistant film. Then the trenches are filled with copper. The wafer is scoured and polished to a flat surface, until the only metal that remains is inside the trenches. The result is a glassy surface inlaid with many meters of glittering copper canals.

The last step is the application of a capping layer of organosilicate—silicon dioxide that has been impregnated with carbon. This layer separates the levels from each other and provides added structural support. Then the process starts anew. Today’s state-of-the-art chips can have up to 10 of these levels. But they are not strictly identical. Instead, they gradually increase in thickness, so that the lowest level of wiring is smaller and more delicate than the topmost level by a factor of eight. At the higher levels of the chip, the insulation is thicker and the wiring more substantial.

But this process no longer suffices. There’s too much drag on the signal traveling down the tiny wires. The culprits are capacitance and resistance. Long, thin wires have more resistance, of course, than short, thick ones. So you can’t do much worse than a nanoscopically thin collection of wire segments that would span a small town if laid end to end. Think of trying to suck a drink through a 2-meter-long cocktail straw. This is why the industry abandoned aluminum for copper wiring—its greater conductivity overcame the resistance of thin wiring.

The other—and bigger—problem is capacitance. When wires are cramped so closely together, the electric field from one wire is felt by neighboring wires, and that creates an unintended capacitor. A capacitor stores electrons, somewhat like a battery. Storing electrons is great for batteries, but it’s bad when those electrons need to get somewhere else. Picture the electrons traveling down the wires in waves. The capacitance in the wire acts like a breaker, damping the waves’ motion and therefore slowing the rate at which the signal can travel from one end of the wire to the other.

A transistor on a digital chip is just a switch that operates at incredibly high speed—2.7 billion times a second in the current generation of microchips. The higher the capacitance between the wires, the more power the transistor needs to operate at that speed. The result is power drain. Reducing capacitance lets the chip use less power to switch at the same speed.

Making the wires thicker isn’t an option, so the only solution is to improve the insulator’s dielectric constant, a measure of the insulation’s ability to concentrate an electric field. The dielectric constant is usually referred to simply as k. The lower the k-value, the better the insulation.

The lowest possible k-value is 1.0, and the only way to achieve that number is with the ideal insulator: vacuum. Natural glass has a k-value of 4.2. When that started to become a problem, researchers began pushing that number lower by “doping” their silicon dioxide—mixing the glass with other elements, like fluorine and carbon. For decades, chip manufacturers have been groaning under the strain of pushing the dielectric constant from 4 to the mid-3s (fluorinated silicon dioxide) to the high 2s (silicon dioxide with severe carbon doping). The problem is that loading the insulator with carbon also changes its density, making the material softer and weaker. Insulation will tolerate only so much doping.

By figuring out how to use vacuum, IBM shot the industry-leading dielectric constant from a spongy 2.7 to an eyebrow-raising 1.9. The resulting microprocessor leapfrogs a full generation in total chip performance without a chip redesign.

So how do you make bubbles full of nothing? There are two ways to make air gaps, and how IBM makes them depends on where in the chip the gaps need to go. For higher levels, the spacing between the wires is less critical, so the vacuum pockets can be carved conventionally—with masks, ultraviolet light, and plasma. As usual, after the interconnect pattern is projected onto the insulation, plasma digs out the channels, and the wiring is laid. That process is then repeated to carve holes into the insulation around the wiring. The level is capped off with organosilicate in a vacuum chamber and, voilà, air gaps. The organosilicate cap layer remains, holding the wiring in place at the top and bottom, but the carved-out spaces between the wires are empty.

This strategy doesn’t work at the lower levels, because the tiny spaces between the wiring don’t tolerate the slightest error. At the lowest levels of the next-generation chips, the width of the insulation between wires is about 50 ­nanometers. Not even the best production processes can create holes inside features that small without nicking the wiring. Thus exposed, the copper would melt under the extreme heat of the plasma and leak through the air gap, fuse with neighboring wires, and ruin the chip. Conventional techniques simply can’t ensure enough precision. Edelstein and Nitta had to invent a different way to make the really, really tiny holes.