As milestones in industrial history go, this one didn't have much in the way of spectacle. Not long ago, in a laboratory in Santa Clara, Calif., five engineers stared into a bucket of chemicals at a silicon wafer as the dull disk gradually grew shiny patches while a clunky-looking motorized polishing pad gently buffed it.

What the event lacked in pizazz it more than made up for in importance. Those little lustrous patches were the first unequivocal sign that researchers had come up with a workable means of solving one of the semiconductor industry's most pressing and intractable problems: how to manufacture faster, more powerful chips without obliterating their vanishingly fine and increasingly fragile features.

The key to meeting this challenge is an esoteric subspecialty known as wafer polishing. Integrated circuits are fabricated in layers. In addition to the few at the bottom that make up the transistors themselves, the top seven or eight of these layers are devoted to the dizzyingly complex maze of ultrafine wires that connect the chip's hundreds of millions of transistors into a functioning circuit. Basically, polishing flattens the surface of silicon wafers in between the steps that lay down the wiring layers during the chip-making process. Without such planarization, the chips would become too riddled with hills and valleys to build more than one or two layers of wiring atop their transistors, limiting the size of a circuit to just a few tens of thousands of transistors.

Mundane as it may sound, wafer polishing was a US $700 million-a-year business in 2003, according to Gartner Dataquest research. It has proved the bedrock on which, directly or indirectly, virtually every major semiconductor advance over the past quarter-century has been built. Wafer polishing has been a key enforcer for the relentless periodic doubling of IC performance known as Moore's Law; it has been a little-known player that has kept the streak going by letting technicians make wafers flat enough to support the multilayered world of wires and their increasingly delicate insulation.

It is this insulation-related challenge, in particular, that has been driving much of the work on polishing lately. Over the past two years, chip makers have been forced to begin insulating on-chip wires with new materials, notably glass doped with fluorine or carbon, and this transition has been described as one of the most difficult the semiconductor industry has ever undergone [see "Fast Films," IEEE Spectrum, February 2003]. The new polishing process developed by Applied Materials Inc., of Santa Clara, Calif., is the most extensive attempt yet to accommodate the new insulation, which is so soft that the current procedure can rip it apart. And chip making will only get more difficult: in order to make faster microprocessors, even softer insulation will have to be integrated into chips. Existing wafer-polishing techniques are simply too rough to do the job.

G. Dan Hutcheson, an industry veteran and CEO of the consulting firm VLSI Research Inc., also in Santa Clara, calls Applied's new technology a "breakthrough" and "a really big step forward." If it performs the way Applied Materials and its customers expect it to, the technology will be one of the key factors that extends Moore's Law into the realm of 4-gigabit memory chips and multibillion-transistor microprocessors.

Magnified pictures of a modern chip and of one from the late 1980s, before wafer polishing, look nothing alike [see photos, "Before and After"]. The new chip has layer after layer of fine wires, or interconnects. Their edges are crisp, clean, and at right angles to one another. The older chip's features look Paleolithic by comparison—two layers of metal that follow a series of rolling hills and valleys. Wafer polishing, more than any other single process, made the difference, enabling multilayer chips that are far more complex, with interconnects fine and fast enough to shuttle bits at blazing speed.