Written in a flash

Flash technology works by storing electrons on a thin layer of polysilicon "afloat" in oxide below a transistor's on-off control gate [see illustration, "Flash Relies on a Floating Gate"]. Called a floating gate, the scrap of polysilicon is electrically isolated by the surrounding oxide from the control gate above and the transistor's channel below. (The channel is the short stretch of the transistor through which charge carriers flow when the transistor is on.) Apply a voltage to the control gate, and if there are no electrons on the floating gate, the device turns on; that could represent a 1. But if there is charge on the floating gate, the device does not turn on, and that could represent a 0.

Reading a flash cell is simple—a matter of measuring whether or not voltage applied to the control gate turns the transistor on. But writing is a more complicated, two-step process.

First, charge is removed from the floating gates of a block of memory cells. Individual blocks can consist of several thousand transistors. Second, the cell is programmed by adding (or not adding) electrons to the floating gate. Many flash technologies program the cell by giving electrons enough energy to blast through the oxide below the floating gate, a process called hot-carrier injection.

This last operation affects charge retention. Electrons shooting through the oxide create defects that let charge leak between the floating gate and the channel. A separate voltage supply of up to 12 V is needed to give the carriers enough energy to plunge through the oxide, and that consumes power and complicates the design.

Enter the electric dipole

Already for sale, ferroelectric RAM products (FRAMs) are the most advanced of the flash challengers. The pioneer, Ramtron International Corp. (Colorado Springs, Colo.), has been selling FRAM chips since 1992. Their memory capacities are low, however, the largest being 256Kb—still a small fraction of the multimegabit chips offered by the major flash memory makers. In current commercial FRAMs, the interconnects that link individual transistors into circuits are 0.5 µm wide and operate at 3 V. Narrower interconnects are desirable so that memory cells may be made smaller and be packed in greater numbers onto an IC. (Ramtron's FRAMs are made by Fujitsu Ltd., Tokyo, which also sells its own FRAM products, mostly as embedded memory in microcontrollers and smart cards.)

The biggest hurdle for FRAM developers is to advance the manufacturing technology to smaller geometries and lower voltages. R and D at Ramtron is aiming at 0.35-µm interconnect widths and 1.8-V operation. And last November, Texas Instruments Inc. (Dallas) announced that it had built a 64Mb FRAM in a standard 0.13-µm CMOS process, using technology licensed from Ramtron.

At the core of an FRAM cell is a capacitor filled with a ferroelectric crystalline material, usually a lead-zirconium-titanate (PZT) compound [see figure, "Ferroelectric Domains Do the Trick for FRAMs"]. Each unit cell (a crystal's basic building block) of a ferroelectric material has a permanent electric field around it. That's because the geometric center of all the electrons in the unit cell is at a different spot from the geometric center of all the protons. It's as though two small particles with equal and opposite charges are separated from each other by a short distance—in short, it is an electric dipole.

Many materials form electric dipoles. But what sets ferroelectric materials apart from other dipolar materials is that millions of dipoles, in a region called a domain, line up to point in the same direction. When an electric field is applied in the opposite direction, the dipoles flip over so that they again point in the direction of the electric field.

Each unit cell of PZT is shaped like an elongated cube. At each of the cube's eight corners is an atom of lead; in the center of each cube face is an oxygen atom; and in the interior of the cube is an atom of either zirconium or titanium. This last has two stable positions, explains Mike Alwais, Ramtron's vice president of FRAM products: "One is near the cube's top face and the other is near the bottom."

Apply an electric field and the atoms in the interiors of all the unit cells in the ferroelectric material move in the field's direction. Remove the field and the atoms stay put. The positions of the atoms in the cubes store the bit of data, a binary 1 or 0.

To read a bit, an electric field is applied. If the atoms are near the cube "floors" and the electric field pushes them to the top, the cell gives off a current pulse. This pulse, representing a stored 1 or 0, is detected by a sense amplifier. Contributing to pulse amplitude are the movements of the interior atoms in the crystals of the ferroelectric material and the capacitor itself. If the atoms are already near their cubes' "ceilings," they don't budge when the field is applied and the cell gives off a smaller pulse, due only to the electric charges stored on the cell capacitor.

Reading an FRAM cell destroys the data stored in its capacitor. So after the bit is read, the sense amplifier writes the data back into the cell, just as in a DRAM.

The FRAM in fact is like the DRAM in every way but one: the DRAM cell's capacitor is of a nonferroelectric material, usually silicon dioxide. When data is stored as charge on the DRAM cell's capacitor, the charge leaks away into the silicon substrate almost immediately—unless it is rewritten several times a second. That requirement drives up power consumption, and of course when the power is turned off, the charge stored in the capacitors quickly disappears.

Because the basic operation and structure of the FRAM and the DRAM are so similar, Alwais expects that FRAMs will eventually run as fast as DRAMs with the same memory capacity and cell size. Today, FRAMs are about 50 percent slower than DRAMs.

Texas Instruments is interested in FRAMs for embedded applications—for example, for on-chip storage of the operating instructions for digital signal processors and microcontrollers, says IEEE Fellow Dennis Buss, Texas Instruments' vice president of R and D. Looking ahead, the biggest obstacle to embedding large memories on a chip is their high power consumption, particularly for wireless applications. "All our tricks to reduce the power used when the memory is idle [static power] are just not adequate for battery-operated systems," says Buss. "That's why we are looking at integrated memory technologies that reduce the static power to zero."

Each of the three new memory technologies—ferroelectric, ferromagnetic, and Ovonic—has zero static power. Texas Instruments has studied the merits of all of them, but has chosen to develop FRAM. One reason for the choice is economic, according to Buss. The desired patterns of semiconductors, insulators, and metals are "stenciled" onto the chips through masks, which are quartz plates covered with chrome stencils. Today's IC chips usually need a succession of 20 to 26 masks, and the more masks, the more complicated and expensive the manufacturing process.

Ferroelectric memory needs only two extra masks added to a chip's manufacturing process, says Buss. So it is much less expensive than magnetic memory, which requires four extra masks. FRAM's maturity is also in its favor. "Fujitsu and Ramtron have shipped more than 100 million chips with up to 256Kb of FRAM," Buss adds. "What we want to do is take it to much higher densities."

At present, Texas Instruments uses flash to fill its nonvolatile memory requirements. Because it would take six to eight extra masks to embed flash with other circuits on the same chip, says Buss, the company finds it cheaper to buy a flash chip, stack it on top of a digital signal-processor chip, and package the two together. "But because FRAM needs only two additional masks, we will be able to build it on the same chip," Buss continues. He expects that embedded FRAM products from his company could be in production by 2005.