A decade from now you won't recognize a transistor even if it's walking toward you up the street, assuming you could see it, of course. The gate length—the marker for gauging how small that CMOS transistor is—will be roughly one-fifth the size of the smallest in production today, only 10 nm instead of today's 50 nm. To get to that size and ensure that the transistor still operates will require many changes:

To improve performance, silicon will be mixed with a semiconductor like germanium to produce a more spacious, strained crystalline structure that lets electric charge carriers move faster.

To reduce the leakage of current that drives up power consumption, gate oxides will be made of materials with more than eight times the dielectric constant (k) of today's silicon dioxide.

For better control of the transistor's on and off states, gates will be of metal, instead of polysilicon.

For better control and (again) to reduce power consumption, gates themselves will be doubled up so that two will do the job a single gate does now.

Among these techniques, strained silicon is the only one to have been commercialized so far. The rest are still at various stages of R and D. High-k dielectrics and metal gates could be next on the market as soon as they can be integrated into the manufacturing process. As for the double-gate devices, the jury is still out. Most researchers believe that they will be necessary when gate lengths shrink to 10 nm. But some think that they could be used earlier in portable applications, such as cellphones and handheld devices, to reduce the number of chips and power dissipation or to add capabilities.